library ieee;
 use ieee.std_logic_1164.all;
 use ieee.std_logic_unsigned.all;

-------------------------------------------------------------------------------
entity latch_ctrl3 is
-------------------------------------------------------------------------------
generic(
   num_of_buffers : integer := 1 -- minimal number is 1 -- 8bit: 1 (0.5ns), 16bit: 3 (1.5ns), 32bit: 
   -- each additional buffer approximately: 0.5ns (0.18um)
);
port( 
      -- General Control: --
      RESET  : in  std_logic;  -- Active  

      -- External input i/f: --
      RI     : in  std_logic;
      AI     : out std_logic;

      -- Latch control i/f: --
      LDO    : out std_logic;
      DI     : in  std_logic;  -- not in use

      -- Internal output i/f: --
      RO     : out std_logic;
      AO     : in  std_logic
);           
-------------------------------------------------------------------------------
end latch_ctrl3 ;
-------------------------------------------------------------------------------

-------------------------------------------------------------------------------
architecture latch_ctrl3_arch of latch_ctrl3 is
-------------------------------------------------------------------------------

component c_element
port( 
      -- Input i/f: --
      A     : in  std_logic;
      B     : in  std_logic;

      -- output i/f: --
      Q     : out std_logic
);           
end component;

component adelay_line
generic(
   num_of_buffers : integer := 1 -- minimal number is 1
);
port( 
      DI  : in   std_logic;   
      DO  : out  std_logic   
);           
end component; 

-- NOR (small)
COMPONENT nr02d1 -- drive x1
PORT(
  a1 : IN std_logic; 
  a2 : IN std_logic;
  zn : OUT std_logic
);
END COMPONENT;

-- NAND -- two input NAND with one inverted input (A)
--component INA24
--port(
--      A                              :	in    std_logic;
--      B                              :	in    std_logic;
--      Q                              :	out   std_logic
--);
--end component;

component nd12d4
port(
      A1                             :	in    std_logic;
      A2                             :	in    std_logic;
      ZN                             :	out   std_logic
);
end component;


signal ro_not, ao_not, ro_int, ai_int, c_to_adel_line : std_logic;
 
begin

--ro_not <= RESET nor ro_int;
--ao_not <= RESET nor AO;
u_ro_not: nr02d1
port map(
      a1 => RESET,
      a2 => ro_int,
      zn => ro_not
);

u_ao_not: nr02d1
port map(
      a1 => RESET,
      a2 => AO,
      zn => ao_not
);

-- In 0.18um Tower the unit delay is 60ps -- here "after" is intended to match this delay of the LDO signal nd12d2 
RO <= transport ro_int after 150 ps;
AI <= ai_int;

u_c_element_in: c_element
port map( 
      A     => RI,
      B     => ro_not,

      Q     => ai_int
); 

u_c_element_out: c_element
port map( 
      A     => ai_int,
      B     => ao_not,

      Q     => c_to_adel_line
); 

u_adelay_line_ldo: adelay_line
generic map(
 num_of_buffers => num_of_buffers
)
port map( 
      DI  => c_to_adel_line,    
      DO  => ro_int 
);  


u_ina24: nd12d4
port map(
      A1   => ro_int, -- inverted. 
      A2   => c_to_adel_line,
      ZN   => LDO
);


-------------------------------------------------------------------------------
end latch_ctrl3_arch;
-------------------------------------------------------------------------------                 

   
-------------------------------------------------------------------------------
configuration  latch_ctrl3_cfg  of latch_ctrl3 is
-------------------------------------------------------------------------------
   for latch_ctrl3_arch
   end for;
-------------------------------------------------------------------------------
end  latch_ctrl3_cfg;              
-------------------------------------------------------------------------------
                 
